1. Field of the Invention
The present invention relates to the field of computer systems, in particular, microprocessor based computer systems. More specifically, the present invention is related to servicing and reducing interrupt latency of transparent system interrupts supported by these computer systems.
2. Background
Today, some computer systems offer system interrupts that are transparent to the operating system and application programs executed by the computer systems. For example, the System Management Interrupt (SMI) provided on the "Intel386.TM. SL Superset" microprocessor system, manufactured by Intel Corporation of Santa Clara, Calif., the assignee of the present invention. A transparent system interrupt is a system interrupt that is non-maskable by the operating system and the application programs. The non-maskable system interrupt has higher priority that all other maskable and non-maskable interrupts. Typically, all other interrupts are blocked while a transparent system interrupt is being serviced.
Referring now to FIG. 1, a flow diagram illustrating the operation flow of a transparent system interrupt is shown. Various mechanisms are typically provided to trigger the non-maskable transparent system interrupt. Once the non-maskable interrupt is detected, the microcode of the non-maskable interrupt typically puts the computer system into an execution mode that is transparent to the operating system. The execution mode is typically made transparent by swapping in a dedicated memory area which is normally not mapped in the computer system's memory address space, block 102. The dedicated memory area is swapped out of the computer system's memory address space when the computer system is subsequently restored to the pre-interrupted state, block 114.
As illustrated in FIG. 1, typically, a resume instruction is provided for taking the computer system out of the transparent execution mode, block 111. The resume instruction is executed by the prestored interrupt handler in the dedicated memory area after it has finished servicing the interrupt. The system state is saved into the dedicated memory area, block 104, before the interrupt handler is given control, block 110. The computer system is restored to the preinterrupted state based on the information saved, block 112.
The majority of the functions performed to service each incidence of the unmaskable system interrupt, block 110, typically can be performed in a relatively short time, thus creating a small and insignificant interrupt latency for the interrupted operating system and application programs. In most cases, the small interrupt latency is not a problem. However, as the application of transparent system interrupt broaden, there are many functions performed to service some of the incidences of the unmaskable system interrupt that may require relatively large amount of time to be performed. In some cases, the interrupted operating system and/or application programs are sensitive to the extended interrupt latency causing them to fail.
Thus, it is desirable if transparent system interrupts can be serviced with minimal interrupt latency, thereby further reducing the remote likelihood of causing the interrupted operating system and application programs to fail. As will be disclosed, these objects and desired results are among the objects and results achieved by the method and apparatus of the present invention for servicing transparent system interrupts and reducing interrupt latency.
For further description of transparent system interrupts and their applications, see product literatures provided by the assignee of the present invention, and the related applications referenced above.